1. Technical Field
The present invention relates to a test pattern of a semiconductor device and a test method using the same, and more particularly, to a test pattern for testing a conductive pattern of a semiconductor device to examine its electric failures, and a test method using the same.
2. Discussion of the Related Art
In order to operate a semiconductor device at required performance requirements, required conditions for alignment, isolation, and electrical connection between its component elements should be satisfied. Further, reduction of a design rule, and formation of a multilayer interconnection structure are required for high integration of a semiconductor device, and thus, the alignment, the isolation, and the electrical connection between its component elements are important factors which directly affect production yield of the semiconductor device. Therefore, the fabrication of a semiconductor device includes various kinds of testing operations in order to determine whether each component element is structured as it is designed before performing each process of the fabrication of a semiconductor device, and to check whether it operates as it should.
When a conductive pattern is formed on a semiconductor substrate, various tests are performed to evaluate the characteristics of the conductive pattern. One of the tests is to examine whether the conductive pattern experiences electrical failures. For example, in the case of forming a polysilicon pattern for forming a gate electrode on a semiconductor substrate, the polysilicon pattern is formed by forming a polysilicon layer on the semiconductor substrate through a chemical vapor deposition (CVD) method, and then performing photolithography and etch processes. However, the polysilicon layer may have electrical defects, for example, short or open conditions due to defects such as particles.
Conventionally, an in-line scanning electron microscope has been used to examine the electrical failures in the conductive pattern such as the polysilicon pattern, or the like. However, examination by the in-line scanning electron microscope has limitations in resolution and accuracy. Further, it takes long to do the test because of a commonly used scanning method, and it is difficult to discriminate important defect types, which may directly effect a reduction in production yield. Therefore, it is required to fabricate a test pattern capable of providing various information for an electrical failure caused in the conductive pattern in a short time. In this connection, a structure of a semiconductor device for detecting a gate defect by an electrical method, and a method of detecting gate defects using the same is disclosed in US Patent Application Publication No. 2003-0102474. Further, a test structure of a semiconductor device for detecting whether a conductive pattern is short or open and locating the position where the short or open is generated, and an evaluation method using the same is disclosed in U.S. Pat. No. 5,877,631.